This disclosure relates to electronic design automation (EDA) tools used to design semiconductor integrated circuit (IC) layouts. In the field of semiconductor manufacturing, a schematic circuit design is typically converted into a physical layout design for an integrated circuit so that the integrated circuit can be fabricated on a semiconductor substrate (a.k.a., wafer). The layout design typically includes a plurality of geometric patterns that are used to create masks. The masks are then used to form patterns on respective layers deposited on the semiconductor wafer to create the desired IC.
IC designers use EDA tools to more rapidly and efficiently create IC layout designs. Such EDA tools typically provide a device library that stores reusable devices (e.g., inverters, op amps, etc.) that can be used or modified in a desired IC layout design. If a designer wishes to modify a previously designed device stored in the device library, the designer can input the name of the device into the EDA tool. Based on the name input by the designer, the EDA tool retrieves the device from the device library, and loads it into a device editor, so the designer can modify one or more layers of the device or select the device if no modifications are necessary. Alternatively, if the designer does not know the name of a device in the device library, the EDA tool allows the designer to draw the layers of the device or cell (e.g., using a stylus or pointing device). This process is repeated until a complete IC layout design is created. An IC typically includes many interconnected devices or cells (e.g., inverter, amplifier, transistor, etc.). Thus, a complete IC layout design may include two or more device layouts (aka, cell layouts), each device layout typically including a plurality of patterned layers to be formed on the wafer, wherein the patterned layers are interconnected to one another in a specified manner to provide the desired device, which constitutes a sub-circuit or cell of the IC.
IC layouts must adhere to strict design rules. A design rule check (DRC) determines whether a particular IC layout satisfies a series of recommended parameters called Design Rules, which are typically specified by semiconductor manufacturers to ensure compatibility with a particular semiconductor manufacturing process. For example, a design rule set might specify certain geometric and connectivity restrictions to ensure sufficient margins to account for variability in semiconductor manufacturing processes. Aside from DRC, other physical verification processes include Layout Versus Schematic (LVS) Checks, XOR Checks, Electrical Rule Checks (ERC) and Antenna Checks.
A successful DRC ensures that the layout conforms to the rules designed for fabricating a device or circuit in accordance with a particular manufacturing process. A successful DRC, however, does not guarantee that the IC layout design actually represents the intended circuit to be fabricated. A LVS check is typically performed on a finished IC layout design to guarantee that the layout design represents the actual circuit the designer desires to fabricate. In other words, LVS checks ensure that the IC layout design will provide all the devices, and connections between the device nodes, required by the circuit schematic of the intended circuit.